-------------------------------- -- BSDL for ADSP-21065L Digital Signal Processor -- in the MBGA package -- -- Created: 06/29/99 - DB -- Modified: 1/17/01 - AA Corrected attribute TAP_SCAN_RESET of TRST -- from signal is false to true -- -- -- entity ADSP_21065L_BGA is generic (PHYSICAL_PIN_MAP : string:="UNDEFINED"); port( ADDR: inout bit_vector(0 to 23); DATA: inout bit_vector(0 to 31); MS: inout bit_vector(0 to 3); RD_B: inout bit; WR_B: inout bit; SW_B: inout bit; ACK: inout bit; TS_B: in bit; IRQ0_B: in bit; IRQ1_B: in bit; IRQ2_B: in bit; FLAG0: inout bit; FLAG1: inout bit; FLAG2: inout bit; FLAG3: inout bit; FLAG4: inout bit; FLAG5: inout bit; FLAG6: inout bit; FLAG7: inout bit; FLAG8: inout bit; FLAG9: inout bit; FLAG10: inout bit; FLAG11: inout bit; HBR_B: in bit; HBG_B: inout bit; CS_B: in bit; REDY: out bit; DMAR1_B: in bit; DMAR2_B: in bit; DMAG1_B: out bit; DMAG2_B: out bit; BR: inout bit_vector(1 to 2); ID0: in bit; ID1: in bit; CPA_B: inout bit; DT0A: out bit; DT0B: out bit; DR0A: in bit; DR0B: in bit; TCLK0: inout bit; RCLK0: inout bit; TFS0: inout bit; RFS0: inout bit; DT1A: out bit; DT1B: out bit; DR1A: in bit; DR1B: in bit; TCLK1: inout bit; RCLK1: inout bit; TFS1: inout bit; RFS1: inout bit; BSEL: in bit; BMS_B: inout bit; CLKIN: in bit; RESET_B: in bit; TCK: in bit; TMS: in bit; TDI: in bit; TDO: out bit; TRST: in bit; EMU: out bit; BMSTR: buffer bit; SDWE_B: inout bit; SDA10: out bit; CAS_B: inout bit; RAS_B: inout bit; DQM: out bit; SDCKE: inout bit; SDCLK0: inout bit; SDCLK1: inout bit; PWM_EVENT0: inout bit; PWM_EVENT1: inout bit; VDD: linkage bit_vector(0 to 21); GND: linkage bit_vector(0 to 34)); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_21065L_BGA: entity is PHYSICAL_PIN_MAP; constant BGA_PACKAGE: PIN_MAP_STRING:= "ADDR: (A4,C5,B5,A5,C6,B6,A6,A7,A8,B7,C7,A9," & "B8,C8,A10,B9,C9,A11,A12,B10,C10,B11,C11,B12)," & "DATA: (P11,N9,M9,P12,N10,M10,P13,N11,L10,M11,N12,N13,M12,L11,M13," & "M14,L12,L13,L14,K11,K13,K12,K14,J14,J12,J13,H14," & "H13,H12,G14,G13,G12)," & "MS: (P6,N7,P7,P8)," & "RD_B: M5," & "WR_B: P4," & "SW_B: P5," & "ACK: M7," & "TS_B: N4," & "IRQ0_B: B3," & "IRQ1_B: D4," & "IRQ2_B: C3," & "FLAG0: B4," & "FLAG1: D5," & "FLAG2: A3," & "FLAG3: C4," & "FLAG4: E14," & "FLAG5: F13," & "FLAG6: F12," & "FLAG7: F14," & "FLAG8: P10," & "FLAG9: P9," & "FLAG10: M8," & "FLAG11: N8," & "HBR_B: K3," & "HBG_B: N2," & "CS_B: M4," & "REDY: N5," & "DMAR1_B: K1," & "DMAR2_B: L1," & "DMAG1_B: M3," & "DMAG2_B: L4," & "BR: (H2,H3)," & "ID0: E11," & "ID1: E13," & "CPA_B: M6," & "DT0A: E3," & "DT0B: E2," & "DR0A: B1," & "DR0B: D3," & "TCLK0: C1," & "RCLK0: C2," & "TFS0: D2," & "RFS0: B2," & "DT1A: G3," & "DT1B: G2," & "DR1A: F3," & "DR1B: F2," & "TCLK1: F1," & "RCLK1: D1," & "TFS1: E1," & "RFS1: E4," & "BSEL: C13," & "BMS_B: D11," & "CLKIN: J1," & "RESET_B: C12," & "TCK: B14," & "TMS: D12," & "TDI: E12," & "TDO: C14," & "TRST: D13," & "EMU: D14," & "BMSTR: N3," & "SDWE_B: K4," & "SDA10: L3," & "CAS_B: L2," & "RAS_B: M1," & "DQM: N1," & "SDCKE: M2," & "SDCLK0: K2," & "SDCLK1: J3," & "PWM_EVENT0: H1," & "PWM_EVENT1: G1," & "VDD: (D6,D7,D8,D9,D10,E5,E10,F4,F11,G4,G11,H4,H11,J4,J11,K5,K10," & "L5,L6,L7,L8,L9)," & "GND: (B13,E6,E7,E8,E9,F5,F6,F7,F8,F9,F10,G5,G6,G7,G8,G9,G10,H5," & "H6,H7,H8,H9,H10,J5,J6,J7,J8,J9,J10,K6,K7,K8,K9,N6,P3)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST: signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (30.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_21065L_BGA: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_21065L_BGA: entity is "BYPASS (00001,00011,00101,00111,01001,01011,01101,01111," & "10001,10011,10101,10111,11001,11011,11101,11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "INTEST (11000)," & "EMULATION (01000,00100,01100,10100,11100,00010,00110,01010," & "01110,10010,10110,11010,11110)"; attribute INSTRUCTION_CAPTURE of ADSP_21065L_BGA: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_21065L_BGA: entity is "EMULATION" ; attribute BOUNDARY_CELLS of ADSP_21065L_BGA: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_21065L_BGA: entity is 285; attribute BOUNDARY_REGISTER of ADSP_21065L_BGA: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_2 , BSEL , input , X ) , " & " 1 ( BC_1 , BMS_B , output3 , X , 4 , 0 , Z ) , " & " 2 ( BC_2 , BMS_B , input , X ) , " & " 3 ( BC_3 , * , internal , X ) , " & " 4 ( BC_1 , * , control , 0 ) , " & " 5 ( BC_2 , RESET_B , input , X ) , " & " 6 ( BC_1 , ADDR(23) , output3 , X , 36 , 0 , Z ) , " & " 7 ( BC_2 , ADDR(23) , input , X ) , " & " 8 ( BC_1 , ADDR(22) , output3 , X , 36 , 0 , Z ) , " & " 9 ( BC_2 , ADDR(22) , input , X ) , " & " 10 ( BC_1 , ADDR(21) , output3 , X , 36 , 0 , Z ) , " & " 11 ( BC_2 , ADDR(21) , input , X ) , " & " 12 ( BC_1 , ADDR(20) , output3 , X , 36 , 0 , Z ) , " & " 13 ( BC_2 , ADDR(20) , input , X ) , " & " 14 ( BC_1 , ADDR(19) , output3 , X , 36 , 0 , Z ) , " & " 15 ( BC_2 , ADDR(19) , input , X ) , " & " 16 ( BC_1 , ADDR(18) , output3 , X , 36 , 0 , Z ) , " & " 17 ( BC_2 , ADDR(18) , input , X ) , " & " 18 ( BC_1 , ADDR(17) , output3 , X , 36 , 0 , Z ) , " & " 19 ( BC_2 , ADDR(17) , input , X ) , " & " 20 ( BC_1 , ADDR(16) , output3 , X , 36 , 0 , Z ) , " & " 21 ( BC_2 , ADDR(16) , input , X ) , " & " 22 ( BC_1 , ADDR(15) , output3 , X , 36 , 0 , Z ) , " & " 23 ( BC_2 , ADDR(15) , input , X ) , " & " 24 ( BC_1 , ADDR(14) , output3 , X , 36 , 0 , Z ) , " & " 25 ( BC_2 , ADDR(14) , input , X ) , " & " 26 ( BC_1 , ADDR(13) , output3 , X , 36 , 0 , Z ) , " & " 27 ( BC_2 , ADDR(13) , input , X ) , " & " 28 ( BC_1 , ADDR(12) , output3 , X , 36 , 0 , Z ) , " & " 29 ( BC_2 , ADDR(12) , input , X ) , " & " 30 ( BC_1 , ADDR(11) , output3 , X , 36 , 0 , Z ) , " & " 31 ( BC_2 , ADDR(11) , input , X ) , " & " 32 ( BC_1 , ADDR(10) , output3 , X , 36 , 0 , Z ) , " & " 33 ( BC_2 , ADDR(10) , input , X ) , " & " 34 ( BC_1 , ADDR(9) , output3 , X , 36 , 0 , Z ) , " & " 35 ( BC_2 , ADDR(9) , input , X ) , " & " 36 ( BC_1 , * , control , 0 ) , " & " 37 ( BC_1 , ADDR(8) , output3 , X , 36 , 0 , Z ) , " & " 38 ( BC_2 , ADDR(8) , input , X ) , " & " 39 ( BC_1 , ADDR(7) , output3 , X , 36 , 0 , Z ) , " & " 40 ( BC_2 , ADDR(7) , input , X ) , " & " 41 ( BC_1 , ADDR(6) , output3 , X , 36 , 0 , Z ) , " & " 42 ( BC_2 , ADDR(6) , input , X ) , " & " 43 ( BC_1 , ADDR(5) , output3 , X , 36 , 0 , Z ) , " & " 44 ( BC_2 , ADDR(5) , input , X ) , " & " 45 ( BC_1 , ADDR(4) , output3 , X , 36 , 0 , Z ) , " & " 46 ( BC_2 , ADDR(4) , input , X ) , " & " 47 ( BC_1 , ADDR(3) , output3 , X , 36 , 0 , Z ) , " & " 48 ( BC_2 , ADDR(3) , input , X ) , " & " 49 ( BC_1 , ADDR(2) , output3 , X , 36 , 0 , Z ) , " & " 50 ( BC_2 , ADDR(2) , input , X ) , " & " 51 ( BC_1 , ADDR(1) , output3 , X , 36 , 0 , Z ) , " & " 52 ( BC_2 , ADDR(1) , input , X ) , " & " 53 ( BC_1 , ADDR(0) , output3 , X , 36 , 0 , Z ) , " & " 54 ( BC_2 , ADDR(0) , input , X ) , " & " 55 ( BC_1 , * , control , 0 ) , " & " 56 ( BC_1 , * , control , 0 ) , " & " 57 ( BC_1 , FLAG0 , output3 , X , 55 , 0 , Z ) , " & " 58 ( BC_2 , FLAG0 , input , X ) , " & " 59 ( BC_1 , FLAG1 , output3 , X , 56 , 0 , Z ) , " & " 60 ( BC_2 , FLAG1 , input , X ) , " & " 61 ( BC_1 , FLAG2 , output3 , X , 63 , 0 , Z ) , " & " 62 ( BC_2 , FLAG2 , input , X ) , " & " 63 ( BC_1 , * , control , 0 ) , " & " 64 ( BC_1 , * , control , 0 ) , " & " 65 ( BC_1 , FLAG3 , output3 , X , 64 , 0 , Z ) , " & " 66 ( BC_2 , FLAG3 , input , X ) , " & " 67 ( BC_3 , * , internal , X ) , " & " 68 ( BC_3 , * , internal , X ) , " & " 69 ( BC_3 , * , internal , X ) , " & " 70 ( BC_3 , * , internal , X ) , " & " 71 ( BC_3 , * , internal , X ) , " & " 72 ( BC_3 , * , internal , X ) , " & " 73 ( BC_2 , IRQ0_B , input , X ) , " & " 74 ( BC_2 , IRQ1_B , input , X ) , " & " 75 ( BC_2 , IRQ2_B , input , X ) , " & " 76 ( BC_3 , * , internal , X ) , " & " 77 ( BC_3 , * , internal , X ) , " & " 78 ( BC_3 , * , internal , X ) , " & " 79 ( BC_1 , RFS0 , output3 , X , 81 , 0 , Z ) , " & " 80 ( BC_2 , RFS0 , input , X ) , " & " 81 ( BC_1 , * , control , 0 ) , " & " 82 ( BC_1 , * , control , 0 ) , " & " 83 ( BC_1 , * , control , 0 ) , " & " 84 ( BC_1 , RCLK0 , output3 , X , 82 , 0 , Z ) , " & " 85 ( BC_2 , RCLK0 , input , X ) , " & " 86 ( BC_2 , DR0A , input , X ) , " & " 87 ( BC_2 , DR0B , input , X ) , " & " 88 ( BC_1 , TFS0 , output3 , X , 83 , 0 , Z ) , " & " 89 ( BC_2 , TFS0 , input , X ) , " & " 90 ( BC_1 , TCLK0 , output3 , X , 92 , 0 , Z ) , " & " 91 ( BC_2 , TCLK0 , input , X ) , " & " 92 ( BC_1 , * , control , 0 ) , " & " 93 ( BC_1 , * , control , 0 ) , " & " 94 ( BC_1 , * , control , 0 ) , " & " 95 ( BC_1 , DT0A , output3 , X , 93 , 0 , Z ) , " & " 96 ( BC_1 , DT0B , output3 , X , 94 , 0 , Z ) , " & " 97 ( BC_1 , RFS1 , output3 , X , 99 , 0 , Z ) , " & " 98 ( BC_2 , RFS1 , input , X ) , " & " 99 ( BC_1 , * , control , 0 ) , " & " 100 ( BC_1 , * , control , 0 ) , " & " 101 ( BC_1 , * , control , 0 ) , " & " 102 ( BC_1 , RCLK1 , output3 , X , 100 , 0 , Z ) , " & " 103 ( BC_2 , RCLK1 , input , X ) , " & " 104 ( BC_2 , DR1A , input , X ) , " & " 105 ( BC_2 , DR1B , input , X ) , " & " 106 ( BC_1 , TFS1 , output3 , X , 101 , 0 , Z ) , " & " 107 ( BC_2 , TFS1 , input , X ) , " & " 108 ( BC_1 , TCLK1 , output3 , X , 110 , 0 , Z ) , " & " 109 ( BC_2 , TCLK1 , input , X ) , " & " 110 ( BC_1 , * , control , 0 ) , " & " 111 ( BC_1 , * , control , 0 ) , " & " 112 ( BC_1 , * , control , 0 ) , " & " 113 ( BC_1 , DT1A , output3 , X , 111 , 0 , Z ) , " & " 114 ( BC_1 , DT1B , output3 , X , 112 , 0 , Z ) , " & " 115 ( BC_1 , PWM_EVENT1 , output3 , X , 117 , 0 , Z ) , " & " 116 ( BC_2 , PWM_EVENT1 , input , X ) , " & " 117 ( BC_1 , * , control , 0 ) , " & " 118 ( BC_1 , * , control , 0 ) , " & " 119 ( BC_1 , * , control , 0 ) , " & " 120 ( BC_1 , * , control , 0 ) , " & " 121 ( BC_1 , PWM_EVENT0 , output3 , X , 118 , 0 , Z ) , " & " 122 ( BC_2 , PWM_EVENT0 , input , X ) , " & " 123 ( BC_1 , BR(1) , output3 , X , 119 , 0 , Z ) , " & " 124 ( BC_2 , BR(1) , input , X ) , " & " 125 ( BC_1 , BR(2) , output3 , X , 120 , 0 , Z ) , " & " 126 ( BC_2 , BR(2) , input , X ) , " & " 127 ( BC_2 , CLKIN , input , X ) , " & " 128 ( BC_1 , * , control , 0 ) , " & " 129 ( BC_1 , SDCLK1 , output3 , X , 128 , 0 , Z ) , " & " 130 ( BC_2 , SDCLK1 , input , X ) , " & " 131 ( BC_1 , * , control , 0 ) , " & " 132 ( BC_1 , SDCLK0 , output3 , X , 131 , 0 , Z ) , " & " 133 ( BC_2 , SDCLK0 , input , X ) , " & " 134 ( BC_2 , DMAR1_B , input , X ) , " & " 135 ( BC_2 , DMAR2_B , input , X ) , " & " 136 ( BC_2 , HBR_B , input , X ) , " & " 137 ( BC_1 , RAS_B , output3 , X , 131 , 0 , Z ) , " & " 138 ( BC_2 , RAS_B , input , X ) , " & " 139 ( BC_1 , CAS_B , output3 , X , 131 , 0 , Z ) , " & " 140 ( BC_2 , CAS_B , input , X ) , " & " 141 ( BC_1 , SDWE_B , output3 , X , 131 , 0 , Z ) , " & " 142 ( BC_2 , SDWE_B , input , X ) , " & " 143 ( BC_1 , DQM , output3 , X , 131 , 0 , Z ) , " & " 144 ( BC_1 , SDCKE , output3 , X , 131 , 0 , Z ) , " & " 145 ( BC_2 , SDCKE , input , X ) , " & " 146 ( BC_1 , SDA10 , output3 , X , 131 , 0 , Z ) , " & " 147 ( BC_1 , * , control , 0 ) , " & " 148 ( BC_1 , DMAG1_B , output3 , X , 153 , 0 , Z ) , " & " 149 ( BC_1 , DMAG2_B , output3 , X , 153 , 0 , Z ) , " & " 150 ( BC_1 , HBG_B , output3 , X , 147 , 0 , Z ) , " & " 151 ( BC_2 , HBG_B , input , X ) , " & " 152 ( BC_1 , BMSTR , output2 , X ) , " & " 153 ( BC_1 , * , control , 0 ) , " & " 154 ( BC_2 , CS_B , input , X ) , " & " 155 ( BC_2 , TS_B , input , X ) , " & " 156 ( BC_3 , * , internal , X ) , " & " 157 ( BC_1 , WR_B , output3 , X , 153 , 0 , Z ) , " & " 158 ( BC_2 , WR_B , input , X ) , " & " 159 ( BC_1 , RD_B , output3 , X , 153 , 0 , Z ) , " & " 160 ( BC_2 , RD_B , input , X ) , " & " 161 ( BC_1 , * , control , 0 ) , " & " 162 ( BC_1 , REDY , output3 , X , 161 , 0 , Z ) , " & " 163 ( BC_1 , SW_B , output3 , X , 153 , 0 , Z ) , " & " 164 ( BC_2 , SW_B , input , X ) , " & " 165 ( BC_1 , CPA_B , output2 , 1 , 165 , 1 , Weak1 ) , " & " 166 ( BC_2 , CPA_B , input , X ) , " & " 167 ( BC_1 , * , control , 0 ) , " & " 168 ( BC_3 , * , internal , X ) , " & " 169 ( BC_1 , ACK , output3 , X , 167 , 0 , Z ) , " & " 170 ( BC_2 , ACK , input , X ) , " & " 171 ( BC_1 , MS(0) , output3 , X , 153 , 0 , Z ) , " & " 172 ( BC_2 , MS(0) , input , X ) , " & " 173 ( BC_1 , MS(1) , output3 , X , 153 , 0 , Z ) , " & " 174 ( BC_2 , MS(1) , input , X ) , " & " 175 ( BC_1 , MS(2) , output3 , X , 153 , 0 , Z ) , " & " 176 ( BC_2 , MS(2) , input , X ) , " & " 177 ( BC_1 , MS(3) , output3 , X , 153 , 0 , Z ) , " & " 178 ( BC_2 , MS(3) , input , X ) , " & " 179 ( BC_1 , FLAG11 , output3 , X , 181 , 0 , Z ) , " & " 180 ( BC_2 , FLAG11 , input , X ) , " & " 181 ( BC_1 , * , control , 0 ) , " & " 182 ( BC_1 , * , control , 0 ) , " & " 183 ( BC_1 , * , control , 0 ) , " & " 184 ( BC_1 , FLAG10 , output3 , X , 182 , 0 , Z ) , " & " 185 ( BC_2 , FLAG10 , input , X ) , " & " 186 ( BC_1 , FLAG9 , output3 , X , 183 , 0 , Z ) , " & " 187 ( BC_2 , FLAG9 , input , X ) , " & " 188 ( BC_1 , FLAG8 , output3 , X , 190 , 0 , Z ) , " & " 189 ( BC_2 , FLAG8 , input , X ) , " & " 190 ( BC_1 , * , control , 0 ) , " & " 191 ( BC_1 , DATA(0) , output3 , X , 209 , 0 , Z ) , " & " 192 ( BC_2 , DATA(0) , input , X ) , " & " 193 ( BC_1 , DATA(1) , output3 , X , 209 , 0 , Z ) , " & " 194 ( BC_2 , DATA(1) , input , X ) , " & " 195 ( BC_1 , DATA(2) , output3 , X , 209 , 0 , Z ) , " & " 196 ( BC_2 , DATA(2) , input , X ) , " & " 197 ( BC_1 , DATA(3) , output3 , X , 209 , 0 , Z ) , " & " 198 ( BC_2 , DATA(3) , input , X ) , " & " 199 ( BC_1 , DATA(4) , output3 , X , 209 , 0 , Z ) , " & " 200 ( BC_2 , DATA(4) , input , X ) , " & " 201 ( BC_1 , DATA(5) , output3 , X , 209 , 0 , Z ) , " & " 202 ( BC_2 , DATA(5) , input , X ) , " & " 203 ( BC_1 , DATA(6) , output3 , X , 209 , 0 , Z ) , " & " 204 ( BC_2 , DATA(6) , input , X ) , " & " 205 ( BC_1 , DATA(7) , output3 , X , 209 , 0 , Z ) , " & " 206 ( BC_2 , DATA(7) , input , X ) , " & " 207 ( BC_1 , DATA(8) , output3 , X , 209 , 0 , Z ) , " & " 208 ( BC_2 , DATA(8) , input , X ) , " & " 209 ( BC_1 , * , control , 0 ) , " & " 210 ( BC_1 , DATA(9) , output3 , X , 209 , 0 , Z ) , " & " 211 ( BC_2 , DATA(9) , input , X ) , " & " 212 ( BC_1 , DATA(10) , output3 , X , 209 , 0 , Z ) , " & " 213 ( BC_2 , DATA(10) , input , X ) , " & " 214 ( BC_1 , DATA(11) , output3 , X , 209 , 0 , Z ) , " & " 215 ( BC_2 , DATA(11) , input , X ) , " & " 216 ( BC_1 , DATA(12) , output3 , X , 209 , 0 , Z ) , " & " 217 ( BC_2 , DATA(12) , input , X ) , " & " 218 ( BC_1 , DATA(13) , output3 , X , 209 , 0 , Z ) , " & " 219 ( BC_2 , DATA(13) , input , X ) , " & " 220 ( BC_3 , * , internal , X ) , " & " 221 ( BC_3 , * , internal , X ) , " & " 222 ( BC_3 , * , internal , X ) , " & " 223 ( BC_3 , * , internal , X ) , " & " 224 ( BC_3 , * , internal , X ) , " & " 225 ( BC_3 , * , internal , X ) , " & " 226 ( BC_1 , DATA(14) , output3 , X , 243 , 0 , Z ) , " & " 227 ( BC_2 , DATA(14) , input , X ) , " & " 228 ( BC_1 , DATA(15) , output3 , X , 243 , 0 , Z ) , " & " 229 ( BC_2 , DATA(15) , input , X ) , " & " 230 ( BC_1 , DATA(16) , output3 , X , 243 , 0 , Z ) , " & " 231 ( BC_2 , DATA(16) , input , X ) , " & " 232 ( BC_1 , DATA(17) , output3 , X , 243 , 0 , Z ) , " & " 233 ( BC_2 , DATA(17) , input , X ) , " & " 234 ( BC_1 , DATA(18) , output3 , X , 243 , 0 , Z ) , " & " 235 ( BC_2 , DATA(18) , input , X ) , " & " 236 ( BC_1 , DATA(19) , output3 , X , 243 , 0 , Z ) , " & " 237 ( BC_2 , DATA(19) , input , X ) , " & " 238 ( BC_1 , DATA(20) , output3 , X , 243 , 0 , Z ) , " & " 239 ( BC_2 , DATA(20) , input , X ) , " & " 240 ( BC_3 , * , internal , X ) , " & " 241 ( BC_3 , * , internal , X ) , " & " 242 ( BC_3 , * , internal , X ) , " & " 243 ( BC_1 , * , control , 0 ) , " & " 244 ( BC_1 , DATA(21) , output3 , X , 243 , 0 , Z ) , " & " 245 ( BC_2 , DATA(21) , input , X ) , " & " 246 ( BC_1 , DATA(22) , output3 , X , 243 , 0 , Z ) , " & " 247 ( BC_2 , DATA(22) , input , X ) , " & " 248 ( BC_1 , DATA(23) , output3 , X , 243 , 0 , Z ) , " & " 249 ( BC_2 , DATA(23) , input , X ) , " & " 250 ( BC_1 , DATA(24) , output3 , X , 243 , 0 , Z ) , " & " 251 ( BC_2 , DATA(24) , input , X ) , " & " 252 ( BC_1 , DATA(25) , output3 , X , 243 , 0 , Z ) , " & " 253 ( BC_2 , DATA(25) , input , X ) , " & " 254 ( BC_1 , DATA(26) , output3 , X , 243 , 0 , Z ) , " & " 255 ( BC_2 , DATA(26) , input , X ) , " & " 256 ( BC_1 , DATA(27) , output3 , X , 243 , 0 , Z ) , " & " 257 ( BC_2 , DATA(27) , input , X ) , " & " 258 ( BC_1 , DATA(28) , output3 , X , 243 , 0 , Z ) , " & " 259 ( BC_2 , DATA(28) , input , X ) , " & " 260 ( BC_1 , DATA(29) , output3 , X , 243 , 0 , Z ) , " & " 261 ( BC_2 , DATA(29) , input , X ) , " & " 262 ( BC_1 , DATA(30) , output3 , X , 243 , 0 , Z ) , " & " 263 ( BC_2 , DATA(30) , input , X ) , " & " 264 ( BC_1 , DATA(31) , output3 , X , 243 , 0 , Z ) , " & " 265 ( BC_2 , DATA(31) , input , X ) , " & " 266 ( BC_1 , FLAG7 , output3 , X , 268 , 0 , Z ) , " & " 267 ( BC_2 , FLAG7 , input , X ) , " & " 268 ( BC_1 , * , control , 0 ) , " & " 269 ( BC_1 , * , control , 0 ) , " & " 270 ( BC_1 , * , control , 0 ) , " & " 271 ( BC_1 , FLAG6 , output3 , X , 269 , 0 , Z ) , " & " 272 ( BC_2 , FLAG6 , input , X ) , " & " 273 ( BC_1 , FLAG5 , output3 , X , 270 , 0 , Z ) , " & " 274 ( BC_2 , FLAG5 , input , X ) , " & " 275 ( BC_1 , FLAG4 , output3 , X , 277 , 0 , Z ) , " & " 276 ( BC_2 , FLAG4 , input , X ) , " & " 277 ( BC_1 , * , control , 0 ) , " & " 278 ( BC_1 , * , control , 0 ) , " & " 279 ( BC_3 , * , internal , X ) , " & " 280 ( BC_3 , * , internal , X ) , " & " 281 ( BC_3 , * , internal , X ) , " & " 282 ( BC_2 , ID1 , input , X ) , " & " 283 ( BC_2 , ID0 , input , X ) , " & " 284 ( BC_1 , EMU , output3 , X , 278 , 0 , Z ) " ; end ADSP_21065L_BGA;