-------------------------------------------------------- -- BSDL for ADSP_2136x Digital Signal Processor -- 136 ball mBGA Package -------------------------------------------------------- entity ADSP_2136x is generic (PHYSICAL_PIN_MAP : string:="UNDEFINED"); port( CLK_CFG0: inout bit; CLK_CFG1: inout bit; BOOTCFG0: inout bit; BOOTCFG1: inout bit; FLAG0: inout bit; FLAG1: inout bit; AD7: inout bit; AD6: inout bit; AD5: inout bit; AD4: inout bit; AD3: inout bit; AD2: inout bit; AD1: inout bit; AD0: inout bit; WR_B: inout bit; RD_B: inout bit; ALE: inout bit; AD15: inout bit; AD14: inout bit; AD13: inout bit; AD12: inout bit; AD11: inout bit; AD10: inout bit; AD9: inout bit; AD8: inout bit; SDATA0A: inout bit; SDATA0B: inout bit; SCLK0: inout bit; SFS0: inout bit; SDATA1A: inout bit; SDATA1B: inout bit; SCLK1: inout bit; SFS1: inout bit; SDATA2A: inout bit; SDATA2B: inout bit; SDATA2C: inout bit; SDATA2D: inout bit; SCLK2: inout bit; SFS2: inout bit; SDATA3A: inout bit; SDATA3B: inout bit; SDATA3C: inout bit; SDATA3D: inout bit; SCLK3: inout bit; SFS3: inout bit; FLAG2: inout bit; FLAG3: inout bit; RESET_B: inout bit; SPIDS: inout bit; SPICK: inout bit; MISO: inout bit; MOSI: inout bit; CLKOUT: inout bit; EMU_B: inout bit; TCK: in bit; TMS: in bit; TDI: in bit; TDO: out bit; TRST_B: in bit; CLKIN: in bit; XTAL2: out bit; AVDD: linkage bit; AVSS: linkage bit; IOVDD: linkage bit_vector(0 to 5); VDD: linkage bit_vector(0 to 12); GND: linkage bit_vector(0 to 53)); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_2136x: entity is PHYSICAL_PIN_MAP; constant BGA_PACKAGE: PIN_MAP_STRING:= "CLK_CFG0: A1," & "CLK_CFG1: B1," & "BOOTCFG0: C2," & "BOOTCFG1: C1," & "FLAG0: F2," & "FLAG1: F1," & "AD7: G1," & "AD6: H1," & "AD5: J1," & "AD4: J2," & "AD3: K1," & "AD2: L1," & "AD1: L2," & "AD0: M1," & "WR_B: M2," & "RD_B: N3," & "ALE: N2," & "AD15: N1," & "AD14: P1," & "AD13: P2," & "AD12: P3," & "AD11: P4," & "AD10: P5," & "AD9: P6," & "AD8: N6," & "SDATA0A: P7," & "SDATA0B: N8," & "SCLK0: P8," & "SFS0: N10," & "SDATA1A: P9," & "SDATA1B: P10," & "SCLK1: P11," & "SFS1: P12," & "SDATA2A: P13," & "SDATA2B: N14," & "SDATA2C: P14," & "SDATA2D: M13," & "SCLK2: M14," & "SFS2: L14," & "SDATA3A: K14," & "SDATA3B: J14," & "SDATA3C: H14," & "SDATA3D: H13," & "SCLK3: G14," & "SFS3: F14," & "FLAG2: F13," & "FLAG3: E14," & "RESET_B: B10," & "SPIDS: A11," & "SPICK: B9," & "MISO: A10," & "MOSI: A9," & "CLKOUT: A6," & "EMU_B: A8," & "TCK: A4," & "TMS: A3," & "TDI: A5," & "TDO: A7," & "TRST_B: B5," & "CLKIN: B4," & "XTAL2: A2," & "AVDD: B7," & "AVSS: B6," & "IOVDD: (B3,B8,G13,H2,N5,N9)," & "VDD: (A12,E1,B11,C14,G2,D1,D14,J13," & "N4,N7,N11,N12,K2)," & "GND: (A13,A14,E2,E4,E5,E6,E9,E10,E11,E13,B2," & "B12,B13,B14,F4,F5,F6,F9,F10,F11,C3,C12," & "C13,D2,D4,D5,D6,D9,D10,D11,D13,J4,J5,J6," & "J9,J10,J11,N13,K4,K5,K6,K9,K10,K11,K13," & "L4,L5,L6,L9,L10,L11,L13,M3,M12)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_2136x: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_2136x: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (01000)," & "INTEST (01100)," & "EMULATION (00100,00110,01110,00010,01010,10000)"; attribute INSTRUCTION_CAPTURE of ADSP_2136x: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_2136x: entity is -- "EMULATION," & -- "MEMTEST"; "EMULATION"; -- attribute INSTRUCTION_USAGE of ADSP_2136x: entity is -- "INTEST (clock CLKIN)"; attribute BOUNDARY_CELLS of ADSP_2136x: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_2136x: entity is 163; attribute BOUNDARY_REGISTER of ADSP_2136x: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_1 , CLK_CFG0 , output3 , X , 1 , 0 , Z ) , " & " 1 ( BC_1 , * , control , 0 ) , " & " 2 ( BC_2 , CLK_CFG0 , input , X ) , " & " 3 ( BC_1 , CLK_CFG1 , output3 , X , 4 , 0 , Z ) , " & " 4 ( BC_1 , * , control , 0 ) , " & " 5 ( BC_2 , CLK_CFG1 , input , X ) , " & " 6 ( BC_1 , BOOTCFG0 , output3 , X , 7 , 0 , Z ) , " & " 7 ( BC_1 , * , control , 0 ) , " & " 8 ( BC_2 , BOOTCFG0 , input , X ) , " & " 9 ( BC_1 , BOOTCFG1 , output3 , X , 10 , 0 , Z ) , " & " 10 ( BC_1 , * , control , 0 ) , " & " 11 ( BC_2 , BOOTCFG1 , input , X ) , " & " 12 ( BC_1 , FLAG0 , output3 , X , 13 , 0 , Z ) , " & " 13 ( BC_1 , * , control , 0 ) , " & " 14 ( BC_2 , FLAG0 , input , X ) , " & " 15 ( BC_1 , FLAG1 , output3 , X , 16 , 0 , Z ) , " & " 16 ( BC_1 , * , control , 0 ) , " & " 17 ( BC_2 , FLAG1 , input , X ) , " & " 18 ( BC_1 , AD7 , output3 , X , 19 , 0 , Z ) , " & " 19 ( BC_1 , * , control , 0 ) , " & " 20 ( BC_2 , AD7 , input , X ) , " & " 21 ( BC_1 , AD6 , output3 , X , 22 , 0 , Z ) , " & " 22 ( BC_1 , * , control , 0 ) , " & " 23 ( BC_2 , AD6 , input , X ) , " & " 24 ( BC_1 , AD5 , output3 , X , 25 , 0 , Z ) , " & " 25 ( BC_1 , * , control , 0 ) , " & " 26 ( BC_2 , AD5 , input , X ) , " & " 27 ( BC_1 , AD4 , output3 , X , 28 , 0 , Z ) , " & " 28 ( BC_1 , * , control , 0 ) , " & " 29 ( BC_2 , AD4 , input , X ) , " & " 30 ( BC_1 , AD3 , output3 , X , 31 , 0 , Z ) , " & " 31 ( BC_1 , * , control , 0 ) , " & " 32 ( BC_2 , AD3 , input , X ) , " & " 33 ( BC_1 , AD2 , output3 , X , 34 , 0 , Z ) , " & " 34 ( BC_1 , * , control , 0 ) , " & " 35 ( BC_2 , AD2 , input , X ) , " & " 36 ( BC_1 , AD1 , output3 , X , 37 , 0 , Z ) , " & " 37 ( BC_1 , * , control , 0 ) , " & " 38 ( BC_2 , AD1 , input , X ) , " & " 39 ( BC_1 , AD0 , output3 , X , 40 , 0 , Z ) , " & " 40 ( BC_1 , * , control , 0 ) , " & " 41 ( BC_2 , AD0 , input , X ) , " & " 42 ( BC_1 , WR_B , output3 , X , 43 , 0 , Z ) , " & " 43 ( BC_1 , * , control , 0 ) , " & " 44 ( BC_2 , WR_B , input , X ) , " & " 45 ( BC_1 , RD_B , output3 , X , 46 , 0 , Z ) , " & " 46 ( BC_1 , * , control , 0 ) , " & " 47 ( BC_2 , RD_B , input , X ) , " & " 48 ( BC_1 , ALE , output3 , X , 49 , 0 , Z ) , " & " 49 ( BC_1 , * , control , 0 ) , " & " 50 ( BC_2 , ALE , input , X ) , " & " 51 ( BC_1 , AD15 , output3 , X , 52 , 0 , Z ) , " & " 52 ( BC_1 , * , control , 0 ) , " & " 53 ( BC_2 , AD15 , input , X ) , " & " 54 ( BC_1 , AD14 , output3 , X , 55 , 0 , Z ) , " & " 55 ( BC_1 , * , control , 0 ) , " & " 56 ( BC_2 , AD14 , input , X ) , " & " 57 ( BC_1 , AD13 , output3 , X , 58 , 0 , Z ) , " & " 58 ( BC_1 , * , control , 0 ) , " & " 59 ( BC_2 , AD13 , input , X ) , " & " 60 ( BC_1 , AD12 , output3 , X , 61 , 0 , Z ) , " & " 61 ( BC_1 , * , control , 0 ) , " & " 62 ( BC_2 , AD12 , input , X ) , " & " 63 ( BC_1 , AD11 , output3 , X , 64 , 0 , Z ) , " & " 64 ( BC_1 , * , control , 0 ) , " & " 65 ( BC_2 , AD11 , input , X ) , " & " 66 ( BC_1 , AD10 , output3 , X , 67 , 0 , Z ) , " & " 67 ( BC_1 , * , control , 0 ) , " & " 68 ( BC_2 , AD10 , input , X ) , " & " 69 ( BC_1 , AD9 , output3 , X , 70 , 0 , Z ) , " & " 70 ( BC_1 , * , control , 0 ) , " & " 71 ( BC_2 , AD9 , input , X ) , " & " 72 ( BC_1 , AD8 , output3 , X , 73 , 0 , Z ) , " & " 73 ( BC_1 , * , control , 0 ) , " & " 74 ( BC_2 , AD8 , input , X ) , " & " 75 ( BC_1 , SDATA0A , output3 , X , 76 , 0 , Z ) , " & " 76 ( BC_1 , * , control , 0 ) , " & " 77 ( BC_2 , SDATA0A , input , X ) , " & " 78 ( BC_1 , SDATA0B , output3 , X , 79 , 0 , Z ) , " & " 79 ( BC_1 , * , control , 0 ) , " & " 80 ( BC_2 , SDATA0B , input , X ) , " & " 81 ( BC_1 , SCLK0 , output3 , X , 82 , 0 , Z ) , " & " 82 ( BC_1 , * , control , 0 ) , " & " 83 ( BC_2 , SCLK0 , input , X ) , " & " 84 ( BC_1 , SFS0 , output3 , X , 85 , 0 , Z ) , " & " 85 ( BC_1 , * , control , 0 ) , " & " 86 ( BC_2 , SFS0 , input , X ) , " & " 87 ( BC_1 , SDATA1A , output3 , X , 88 , 0 , Z ) , " & " 88 ( BC_1 , * , control , 0 ) , " & " 89 ( BC_2 , SDATA1A , input , X ) , " & " 90 ( BC_1 , SDATA1B , output3 , X , 91 , 0 , Z ) , " & " 91 ( BC_1 , * , control , 0 ) , " & " 92 ( BC_2 , SDATA1B , input , X ) , " & " 93 ( BC_1 , SCLK1 , output3 , X , 94 , 0 , Z ) , " & " 94 ( BC_1 , * , control , 0 ) , " & " 95 ( BC_2 , SCLK1 , input , X ) , " & " 96 ( BC_1 , SFS1 , output3 , X , 97 , 0 , Z ) , " & " 97 ( BC_1 , * , control , 0 ) , " & " 98 ( BC_2 , SFS1 , input , X ) , " & " 99 ( BC_1 , SDATA2A , output3 , X , 100 , 0 , Z ) , " & " 100 ( BC_1 , * , control , 0 ) , " & " 101 ( BC_2 , SDATA2A , input , X ) , " & " 102 ( BC_1 , SDATA2B , output3 , X , 103 , 0 , Z ) , " & " 103 ( BC_1 , * , control , 0 ) , " & " 104 ( BC_2 , SDATA2B , input , X ) , " & " 105 ( BC_1 , SDATA2C , output3 , X , 106 , 0 , Z ) , " & " 106 ( BC_1 , * , control , 0 ) , " & " 107 ( BC_2 , SDATA2C , input , X ) , " & " 108 ( BC_1 , SDATA2D , output3 , X , 109 , 0 , Z ) , " & " 109 ( BC_1 , * , control , 0 ) , " & " 110 ( BC_2 , SDATA2D , input , X ) , " & " 111 ( BC_1 , SCLK2 , output3 , X , 112 , 0 , Z ) , " & " 112 ( BC_1 , * , control , 0 ) , " & " 113 ( BC_2 , SCLK2 , input , X ) , " & " 114 ( BC_1 , SFS2 , output3 , X , 115 , 0 , Z ) , " & " 115 ( BC_1 , * , control , 0 ) , " & " 116 ( BC_2 , SFS2 , input , X ) , " & " 117 ( BC_1 , SDATA3A , output3 , X , 118 , 0 , Z ) , " & " 118 ( BC_1 , * , control , 0 ) , " & " 119 ( BC_2 , SDATA3A , input , X ) , " & " 120 ( BC_1 , SDATA3B , output3 , X , 121 , 0 , Z ) , " & " 121 ( BC_1 , * , control , 0 ) , " & " 122 ( BC_2 , SDATA3B , input , X ) , " & " 123 ( BC_1 , SDATA3C , output3 , X , 124 , 0 , Z ) , " & " 124 ( BC_1 , * , control , 0 ) , " & " 125 ( BC_2 , SDATA3C , input , X ) , " & " 126 ( BC_1 , SDATA3D , output3 , X , 127 , 0 , Z ) , " & " 127 ( BC_1 , * , control , 0 ) , " & " 128 ( BC_2 , SDATA3D , input , X ) , " & " 129 ( BC_1 , SCLK3 , output3 , X , 130 , 0 , Z ) , " & " 130 ( BC_1 , * , control , 0 ) , " & " 131 ( BC_2 , SCLK3 , input , X ) , " & " 132 ( BC_1 , SFS3 , output3 , X , 133 , 0 , Z ) , " & " 133 ( BC_1 , * , control , 0 ) , " & " 134 ( BC_2 , SFS3 , input , X ) , " & " 135 ( BC_1 , FLAG2 , output3 , X , 136 , 0 , Z ) , " & " 136 ( BC_1 , * , control , 0 ) , " & " 137 ( BC_2 , FLAG2 , input , X ) , " & " 138 ( BC_1 , FLAG3 , output3 , X , 139 , 0 , Z ) , " & " 139 ( BC_1 , * , control , 0 ) , " & " 140 ( BC_2 , FLAG3 , input , X ) , " & " 141 ( BC_1 , RESET_B , output3 , X , 142 , 0 , Z ) , " & " 142 ( BC_1 , * , control , 0 ) , " & " 143 ( BC_2 , RESET_B , input , X ) , " & " 144 ( BC_1 , SPIDS , output3 , X , 145 , 0 , Z ) , " & " 145 ( BC_1 , * , control , 0 ) , " & " 146 ( BC_2 , SPIDS , input , X ) , " & " 147 ( BC_1 , SPICK , output3 , X , 148 , 0 , Z ) , " & " 148 ( BC_1 , * , control , 0 ) , " & " 149 ( BC_2 , SPICK , input , X ) , " & " 150 ( BC_1 , MISO , output3 , X , 151 , 0 , Z ) , " & " 151 ( BC_1 , * , control , 0 ) , " & " 152 ( BC_2 , MISO , input , X ) , " & " 153 ( BC_1 , MOSI , output3 , X , 154 , 0 , Z ) , " & " 154 ( BC_1 , * , control , 0 ) , " & " 155 ( BC_2 , MOSI , input , X ) , " & " 156 ( BC_1 , CLKOUT , output3 , X , 157 , 0 , Z ) , " & " 157 ( BC_1 , * , control , 0 ) , " & " 158 ( BC_2 , CLKOUT , input , X ) , " & " 159 ( BC_1 , EMU_B , output3 , X , 160 , 0 , Z ) , " & " 160 ( BC_1 , * , control , 0 ) , " & " 161 ( BC_2 , EMU_B , input , X ) , " & " 162 ( BC_3 , * , internal , X ) " ; end ADSP_2136x;