---------------------------------------------------------------------- -- BSDL file for ADSP_BF532 Digital Signal Processor in LQFP Package -- -- Revision 0.1: Date: 2/6/2004 - Changed EMU_B from out to linkage -- Changed ADSP_21532 to ADSP_BF532 -- Date: 9/16/2003- Initial ---------------------------------------------------------------------- entity ADSP_BF532 is generic (PHYSICAL_PIN_MAP : string:="LQFP_PACKAGE"); port( ADDR: out bit_vector(1 to 19); AMS_B: out bit_vector(0 to 3); AOE_B: out bit; ARDY: in bit; ARE_B: out bit; AWE_B: out bit; ABE_B: out bit_vector(0 to 1); BG_B: buffer bit; BGH_B: buffer bit; BMODE: in bit_vector(0 to 1); BR_B: in bit; DATA: inout bit_vector(0 to 15); DR0PRI: in bit; DR0SEC: in bit; DR1PRI: in bit; DR1SEC: in bit; DT0PRI: out bit; DT0SEC: out bit; DT1PRI: out bit; DT1SEC: out bit; MISO: inout bit; MOSI: inout bit; NMI: in bit; PF: inout bit_vector(0 to 15); PP_CLK: in bit; PP: inout bit_vector(0 to 3); RESET_B:in bit; RFS0: inout bit; RFS1: inout bit; RSCLK0: inout bit; RSCLK1: inout bit; TSCLK0: inout bit; TSCLK1: inout bit; CLKOUT: out bit; RX: in bit; TX: buffer bit; SA10: out bit; SCAS_B: out bit; SCK: inout bit; SCKE: out bit; SMS_B: out bit; SRAS_B: out bit; SWE_B: out bit; TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit; TRST_B: in bit; EMU_B: linkage bit; TEST: in bit; TFS0: inout bit; TFS1: inout bit; TMR0: inout bit; TMR1: inout bit; TMR2: inout bit; RTXI: linkage bit; RTXO: linkage bit; VDD_INT:linkage bit_vector(0 to 7); VDD_EXT:linkage bit_vector(0 to 13); GND: linkage bit_vector(0 to 35); VDD_RTC:linkage bit; CLKIN: linkage bit; XTAL: linkage bit; VROUT: linkage bit_vector(0 to 1)); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_BF532: entity is PHYSICAL_PIN_MAP; constant LQFP_PACKAGE: PIN_MAP_STRING:= "ADDR: (149,148,147,146,142,141,140,139,138,137,136,135,127," & "126,125,124,123,122,121)," & "DATA: (116,115,114,113,112,110,109,108,105,104,103,102,101,100,99,98)," & "AMS_B: (161,160,159,158)," & "AOE_B: 154," & "ARDY: 162," & "ARE_B: 153," & "AWE_B: 152," & "ABE_B: (151,150)," & "BG_B: 119," & "BGH_B: 120," & "BMODE: (96,95)," & "BR_B: 163," & "DR0PRI: 74," & "DR0SEC: 73," & "DR1PRI: 63," & "DR1SEC: 62," & "DT0PRI: 68," & "DT0SEC: 67," & "DT1PRI: 59," & "DT1SEC: 58," & "MISO: 54," & "MOSI: 55," & "NMI: 14," & "PF: (51,50,49,48,47,46,38,37,36,35,34,33,32,29,28,27)," & "PP_CLK: 21," & "PP: (22,23,24,26)," & "RESET_B:13," & "RFS0: 75," & "RFS1: 64," & "RSCLK0: 76," & "RSCLK1: 65," & "TSCLK0: 72," & "TSCLK1: 61," & "CLKOUT: 169," & "RX: 82," & "TX: 81," & "SA10: 164," & "SCAS_B: 166," & "SCK: 53," & "SCKE: 173," & "SMS_B: 172," & "SRAS_B: 167," & "SWE_B: 165," & "TCK: 94," & "TDI: 86," & "TDO: 87," & "TMS: 85," & "TRST_B: 84," & "EMU_B: 83," & "TEST: 97," & "TFS0: 69," & "TFS1: 60," & "TMR0: 79," & "TMR1: 78," & "TMR2: 77," & "RTXI: 17," & "RTXO: 16," & "VDD_INT: (25,52,66,80,111,143,157,168)," & "VDD_EXT: (6,12,20,31,45,57,71,93,107,118,134,145,156,171)," & "GND: (1,2,3,7,8,9,15,19,30,39,40,41,42,43,44,56,70,88,89,90,91,92," & "106,117,128,129,130,131,132,133,144,155,170,174,175,176)," & "VDD_RTC: 18," & "CLKIN: 10," & "XTAL: 11," & "VROUT: (5,4)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_BF532: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_BF532: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "IDCODE (00010)," & "MEMBIST (01010)," & "EMULATION (00100,10100,01000,11110,01100)," & "CUSTOMER_KEY (10110)," & "TESTKEY (00110)"; attribute INSTRUCTION_CAPTURE of ADSP_BF532: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_BF532: entity is "EMULATION," & "MEMBIST," & "CUSTOMER_KEY," & "TESTKEY" ; attribute IDCODE_REGISTER of ADSP_BF532: entity is "0010" & -- Version "0010011110100101" & "00001100101" & "1"; attribute BOUNDARY_CELLS of ADSP_BF532: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; -- BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_BF532: entity is 197; attribute BOUNDARY_REGISTER of ADSP_BF532: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_1 , BG_B , output2 , X ) , " & " 1 ( BC_1 , BGH_B , output2 , X ) , " & " 2 ( BC_1 , ADDR(19) , output3 , X , 17 , 0 , Z ) , " & " 3 ( BC_1 , ADDR(18) , output3 , X , 17 , 0 , Z ) , " & " 4 ( BC_1 , ADDR(17) , output3 , X , 17 , 0 , Z ) , " & " 5 ( BC_1 , ADDR(16) , output3 , X , 17 , 0 , Z ) , " & " 6 ( BC_1 , ADDR(15) , output3 , X , 17 , 0 , Z ) , " & " 7 ( BC_1 , ADDR(14) , output3 , X , 17 , 0 , Z ) , " & " 8 ( BC_1 , ADDR(13) , output3 , X , 17 , 0 , Z ) , " & " 9 ( BC_1 , ADDR(12) , output3 , X , 17 , 0 , Z ) , " & " 10 ( BC_1 , ADDR(11) , output3 , X , 17 , 0 , Z ) , " & " 11 ( BC_1 , ADDR(10) , output3 , X , 17 , 0 , Z ) , " & " 12 ( BC_1 , ADDR(9) , output3 , X , 17 , 0 , Z ) , " & " 13 ( BC_1 , ADDR(8) , output3 , X , 17 , 0 , Z ) , " & " 14 ( BC_1 , ADDR(7) , output3 , X , 17 , 0 , Z ) , " & " 15 ( BC_1 , ADDR(6) , output3 , X , 17 , 0 , Z ) , " & " 16 ( BC_1 , ADDR(5) , output3 , X , 17 , 0 , Z ) , " & " 17 ( BC_1 , * , control , 0 ) , " & " 18 ( BC_1 , ADDR(4) , output3 , X , 17 , 0 , Z ) , " & " 19 ( BC_1 , ADDR(3) , output3 , X , 17 , 0 , Z ) , " & " 20 ( BC_1 , ADDR(2) , output3 , X , 17 , 0 , Z ) , " & " 21 ( BC_1 , ADDR(1) , output3 , X , 17 , 0 , Z ) , " & " 22 ( BC_1 , ABE_B(1) , output3 , X , 17 , 0 , Z ) , " & " 23 ( BC_1 , ABE_B(0) , output3 , X , 17 , 0 , Z ) , " & " 24 ( BC_1 , AWE_B , output3 , X , 27 , 0 , Z ) , " & " 25 ( BC_1 , ARE_B , output3 , X , 27 , 0 , Z ) , " & " 26 ( BC_1 , AOE_B , output3 , X , 27 , 0 , Z ) , " & " 27 ( BC_1 , * , control , 0 ) , " & " 28 ( BC_1 , AMS_B(3) , output3 , X , 27 , 0 , Z ) , " & " 29 ( BC_1 , AMS_B(2) , output3 , X , 27 , 0 , Z ) , " & " 30 ( BC_1 , AMS_B(1) , output3 , X , 27 , 0 , Z ) , " & " 31 ( BC_1 , AMS_B(0) , output3 , X , 27 , 0 , Z ) , " & " 32 ( BC_2 , ARDY , input , X ) , " & " 33 ( BC_2 , BR_B , input , X ) , " & " 34 ( BC_1 , SA10 , output3 , X , 39 , 0 , Z ) , " & " 35 ( BC_1 , SWE_B , output3 , X , 39 , 0 , Z ) , " & " 36 ( BC_1 , SCAS_B , output3 , X , 39 , 0 , Z ) , " & " 37 ( BC_1 , SRAS_B , output3 , X , 39 , 0 , Z ) , " & " 38 ( BC_1 , CLKOUT , output3 , X , 39 , 0 , Z ) , " & " 39 ( BC_1 , * , control , 0 ) , " & " 40 ( BC_1 , SMS_B , output3 , X , 39 , 0 , Z ) , " & " 41 ( BC_1 , SCKE , output3 , X , 39 , 0 , Z ) , " & " 42 ( BC_2 , RESET_B , input , X ) , " & " 43 ( BC_2 , NMI , input , X ) , " & " 44 ( BC_2 , PP_CLK , input , X ) , " & " 45 ( BC_2 , PP(0) , input , X ) , " & " 46 ( BC_1 , PP(0) , output3 , X , 47 , 0 , Z ) , " & " 47 ( BC_1 , * , control , 0 ) , " & " 48 ( BC_2 , PP(1) , input , X ) , " & " 49 ( BC_1 , PP(1) , output3 , X , 50 , 0 , Z ) , " & " 50 ( BC_1 , * , control , 0 ) , " & " 51 ( BC_2 , PP(2) , input , X ) , " & " 52 ( BC_1 , PP(2) , output3 , X , 53 , 0 , Z ) , " & " 53 ( BC_1 , * , control , 0 ) , " & " 54 ( BC_2 , PP(3) , input , X ) , " & " 55 ( BC_1 , PP(3) , output3 , X , 56 , 0 , Z ) , " & " 56 ( BC_1 , * , control , 0 ) , " & " 57 ( BC_2 , PF(15) , input , X ) , " & " 58 ( BC_1 , PF(15) , output3 , X , 59 , 0 , Z ) , " & " 59 ( BC_1 , * , control , 0 ) , " & " 60 ( BC_2 , PF(14) , input , X ) , " & " 61 ( BC_1 , PF(14) , output3 , X , 62 , 0 , Z ) , " & " 62 ( BC_1 , * , control , 0 ) , " & " 63 ( BC_2 , PF(13) , input , X ) , " & " 64 ( BC_1 , PF(13) , output3 , X , 65 , 0 , Z ) , " & " 65 ( BC_1 , * , control , 0 ) , " & " 66 ( BC_2 , PF(12) , input , X ) , " & " 67 ( BC_1 , PF(12) , output3 , X , 68 , 0 , Z ) , " & " 68 ( BC_1 , * , control , 0 ) , " & " 69 ( BC_2 , PF(11) , input , X ) , " & " 70 ( BC_1 , PF(11) , output3 , X , 71 , 0 , Z ) , " & " 71 ( BC_1 , * , control , 0 ) , " & " 72 ( BC_2 , PF(10) , input , X ) , " & " 73 ( BC_1 , PF(10) , output3 , X , 74 , 0 , Z ) , " & " 74 ( BC_1 , * , control , 0 ) , " & " 75 ( BC_2 , PF(9) , input , X ) , " & " 76 ( BC_1 , PF(9) , output3 , X , 77 , 0 , Z ) , " & " 77 ( BC_1 , * , control , 0 ) , " & " 78 ( BC_2 , PF(8) , input , X ) , " & " 79 ( BC_1 , PF(8) , output3 , X , 80 , 0 , Z ) , " & " 80 ( BC_1 , * , control , 0 ) , " & " 81 ( BC_2 , PF(7) , input , X ) , " & " 82 ( BC_1 , PF(7) , output3 , X , 83 , 0 , Z ) , " & " 83 ( BC_1 , * , control , 0 ) , " & " 84 ( BC_2 , PF(6) , input , X ) , " & " 85 ( BC_1 , PF(6) , output3 , X , 86 , 0 , Z ) , " & " 86 ( BC_1 , * , control , 0 ) , " & " 87 ( BC_2 , PF(5) , input , X ) , " & " 88 ( BC_1 , PF(5) , output3 , X , 89 , 0 , Z ) , " & " 89 ( BC_1 , * , control , 0 ) , " & " 90 ( BC_2 , PF(4) , input , X ) , " & " 91 ( BC_1 , PF(4) , output3 , X , 92 , 0 , Z ) , " & " 92 ( BC_1 , * , control , 0 ) , " & " 93 ( BC_2 , PF(3) , input , X ) , " & " 94 ( BC_1 , PF(3) , output3 , X , 95 , 0 , Z ) , " & " 95 ( BC_1 , * , control , 0 ) , " & " 96 ( BC_2 , PF(2) , input , X ) , " & " 97 ( BC_1 , PF(2) , output3 , X , 98 , 0 , Z ) , " & " 98 ( BC_1 , * , control , 0 ) , " & " 99 ( BC_2 , PF(1) , input , X ) , " & " 100 ( BC_1 , PF(1) , output3 , X , 101 , 0 , Z ) , " & " 101 ( BC_1 , * , control , 0 ) , " & " 102 ( BC_2 , PF(0) , input , X ) , " & " 103 ( BC_1 , PF(0) , output3 , X , 104 , 0 , Z ) , " & " 104 ( BC_1 , * , control , 0 ) , " & " 105 ( BC_2 , SCK , input , X ) , " & " 106 ( BC_1 , SCK , output3 , X , 107 , 0 , Z ) , " & " 107 ( BC_1 , * , control , 0 ) , " & " 108 ( BC_2 , MISO , input , X ) , " & " 109 ( BC_1 , MISO , output3 , X , 110 , 0 , Z ) , " & " 110 ( BC_1 , * , control , 0 ) , " & " 111 ( BC_2 , MOSI , input , X ) , " & " 112 ( BC_1 , MOSI , output3 , X , 113 , 0 , Z ) , " & " 113 ( BC_1 , * , control , 0 ) , " & " 114 ( BC_1 , DT1SEC , output3 , X , 115 , 0 , Z ) , " & " 115 ( BC_1 , * , control , 0 ) , " & " 116 ( BC_1 , DT1PRI , output3 , X , 117 , 0 , Z ) , " & " 117 ( BC_1 , * , control , 0 ) , " & " 118 ( BC_2 , TFS1 , input , X ) , " & " 119 ( BC_1 , TFS1 , output3 , X , 120 , 0 , Z ) , " & " 120 ( BC_1 , * , control , 0 ) , " & " 121 ( BC_2 , TSCLK1 , input , X ) , " & " 122 ( BC_1 , TSCLK1 , output3 , X , 123 , 0 , Z ) , " & " 123 ( BC_1 , * , control , 0 ) , " & " 124 ( BC_2 , DR1SEC , input , X ) , " & " 125 ( BC_2 , DR1PRI , input , X ) , " & " 126 ( BC_2 , RFS1 , input , X ) , " & " 127 ( BC_1 , RFS1 , output3 , X , 128 , 0 , Z ) , " & " 128 ( BC_1 , * , control , 0 ) , " & " 129 ( BC_2 , RSCLK1 , input , X ) , " & " 130 ( BC_1 , RSCLK1 , output3 , X , 131 , 0 , Z ) , " & " 131 ( BC_1 , * , control , 0 ) , " & " 132 ( BC_1 , DT0SEC , output3 , X , 133 , 0 , Z ) , " & " 133 ( BC_1 , * , control , 0 ) , " & " 134 ( BC_1 , DT0PRI , output3 , X , 135 , 0 , Z ) , " & " 135 ( BC_1 , * , control , 0 ) , " & " 136 ( BC_2 , TFS0 , input , X ) , " & " 137 ( BC_1 , TFS0 , output3 , X , 138 , 0 , Z ) , " & " 138 ( BC_1 , * , control , 0 ) , " & " 139 ( BC_2 , TSCLK0 , input , X ) , " & " 140 ( BC_1 , TSCLK0 , output3 , X , 141 , 0 , Z ) , " & " 141 ( BC_1 , * , control , 0 ) , " & " 142 ( BC_2 , DR0SEC , input , X ) , " & " 143 ( BC_2 , DR0PRI , input , X ) , " & " 144 ( BC_2 , RFS0 , input , X ) , " & " 145 ( BC_1 , RFS0 , output3 , X , 146 , 0 , Z ) , " & " 146 ( BC_1 , * , control , 0 ) , " & " 147 ( BC_2 , RSCLK0 , input , X ) , " & " 148 ( BC_1 , RSCLK0 , output3 , X , 149 , 0 , Z ) , " & " 149 ( BC_1 , * , control , 0 ) , " & " 150 ( BC_2 , TMR2 , input , X ) , " & " 151 ( BC_1 , TMR2 , output3 , X , 152 , 0 , Z ) , " & " 152 ( BC_1 , * , control , 0 ) , " & " 153 ( BC_2 , TMR1 , input , X ) , " & " 154 ( BC_1 , TMR1 , output3 , X , 155 , 0 , Z ) , " & " 155 ( BC_1 , * , control , 0 ) , " & " 156 ( BC_2 , TMR0 , input , X ) , " & " 157 ( BC_1 , TMR0 , output3 , X , 158 , 0 , Z ) , " & " 158 ( BC_1 , * , control , 0 ) , " & " 159 ( BC_1 , TX , output2 , X ) , " & " 160 ( BC_2 , RX , input , X ) , " & " 161 ( BC_2 , BMODE(1) , input , X ) , " & " 162 ( BC_2 , BMODE(0) , input , X ) , " & " 163 ( BC_2 , TEST , input , X ) , " & " 164 ( BC_2 , DATA(15) , input , X ) , " & " 165 ( BC_1 , DATA(15) , output3 , X , 196 , 0 , Z ) , " & " 166 ( BC_2 , DATA(14) , input , X ) , " & " 167 ( BC_1 , DATA(14) , output3 , X , 196 , 0 , Z ) , " & " 168 ( BC_2 , DATA(13) , input , X ) , " & " 169 ( BC_1 , DATA(13) , output3 , X , 196 , 0 , Z ) , " & " 170 ( BC_2 , DATA(12) , input , X ) , " & " 171 ( BC_1 , DATA(12) , output3 , X , 196 , 0 , Z ) , " & " 172 ( BC_2 , DATA(11) , input , X ) , " & " 173 ( BC_1 , DATA(11) , output3 , X , 196 , 0 , Z ) , " & " 174 ( BC_2 , DATA(10) , input , X ) , " & " 175 ( BC_1 , DATA(10) , output3 , X , 196 , 0 , Z ) , " & " 176 ( BC_2 , DATA(9) , input , X ) , " & " 177 ( BC_1 , DATA(9) , output3 , X , 196 , 0 , Z ) , " & " 178 ( BC_2 , DATA(8) , input , X ) , " & " 179 ( BC_1 , DATA(8) , output3 , X , 196 , 0 , Z ) , " & " 180 ( BC_2 , DATA(7) , input , X ) , " & " 181 ( BC_1 , DATA(7) , output3 , X , 196 , 0 , Z ) , " & " 182 ( BC_2 , DATA(6) , input , X ) , " & " 183 ( BC_1 , DATA(6) , output3 , X , 196 , 0 , Z ) , " & " 184 ( BC_2 , DATA(5) , input , X ) , " & " 185 ( BC_1 , DATA(5) , output3 , X , 196 , 0 , Z ) , " & " 186 ( BC_2 , DATA(4) , input , X ) , " & " 187 ( BC_1 , DATA(4) , output3 , X , 196 , 0 , Z ) , " & " 188 ( BC_2 , DATA(3) , input , X ) , " & " 189 ( BC_1 , DATA(3) , output3 , X , 196 , 0 , Z ) , " & " 190 ( BC_2 , DATA(2) , input , X ) , " & " 191 ( BC_1 , DATA(2) , output3 , X , 196 , 0 , Z ) , " & " 192 ( BC_2 , DATA(1) , input , X ) , " & " 193 ( BC_1 , DATA(1) , output3 , X , 196 , 0 , Z ) , " & " 194 ( BC_2 , DATA(0) , input , X ) , " & " 195 ( BC_1 , DATA(0) , output3 , X , 196 , 0 , Z ) , " & " 196 ( BC_1 , * , control , 0 )"; end ADSP_BF532;